The present invention relates to a method of manufacturing a semiconductor device.
When a field effect semiconductor device such as a MOSFET is miniaturized in accordance with a known scale-down scheme, the concentration of dopant is the semiconductor substrate increases and the junction depth becomes very shallow. Meanwhile, alignment precision in the lithography technique is not improved in proportion to miniaturization of MOSFETs. For this reason, in MOSFETs having a normal structure, relative alignment margins between the gate and a contact and between an isolation region and a contact must be increased upon miniaturization of the MOSFETs. Therefore, the area of a diffused layer cannot be decreased in proportion to the gate area of a MOSFET. As the miniaturization progresses, a relative parasitic capacitance caused by the capacitance of the diffused layer increases, and interferes with improvement in performance upon miniaturization. Since the junction depth is very shallow, a metal material of an upper electrode may often extend through a junction under a contact hole. Such problems must be solved in order to realize LSIs of higher density and higher operating speed.
A silicon on insulator (SOI) has been conveniently used in an attempt to solve the problem. In the device using SOI, a semiconductor layer on an insulating substrate serves as an active layer, i.e., source, drain and channel regions are formed in the semiconductor layer on an insulating substrate.
Another conventional way to solve the problems is to make the device in a special structure in which the main source and drain regions are formed on a thick field insulating film. This structure is different from SOI in that the channel region is electrically connected to the semiconductor substrate and is not electrically floating.
For example, in the former method, when the SOI substrate is used, the parasitic capacitance can be reduced by the SOI substrate itself, a junction breakdown under the contact hole cannot occur, and device isolation can be perfectly performed, but the electronic characteristics of the resulting device are unstable due to variations in substrate potential. A very thin semiconductor layer which is formed on the insulating film and has the same depth as the junction depth has poor crystallinity, and its formation process is complicated.
In the latter method, when the main source and drain regions are formed on a region of the thick field insulating film, the metal electrode cannot break the junction under the contact hole region, and a parasitic capacitance of the diffused layer can be reduced, but the following problems are encountered. In this method, in order to form a miniaturized MOSFET and to reduce the parasitic capacitance a, high-precision alignment between a gate pattern and a field insulating film is required. If an alignment margin is too large, a junction area contacting the substrate increases accordingly, and the parasitic capacitance undesirably increases. In addition, since the mask alignment margin is required, any increase in integration density in LSI is limited. When the main source and drain regions are formed on the thick field insulating film, a silicon dioxide film is used as the field insulating film. Therefore, a silicon thin film formed on the field insulating film cannot have the desired characteristics. More specifically, when silicon is deposited on silicon dioxide under the condition wherein an excellent epitaxial crystal can be grown on a monocrystalline substrate (e.g., by the CVD method at high temperatures of 700.degree. C. or higher), the silicon on the silicon dioxide has a roughened surface due to its granular growth. This is estimated to be caused because an interfacial free energy between the silicon dioxide film and the silicon is large, and the silicon reacts with the silicon dioxide to increase the size of the silicon crystal grains.
For this reason, the thickness of the silicon thin film deposited on the silicon dioxide cannot be decreased (below 0.3 .mu.m), and it is difficult to miniaturize a device. Conversely, under the deposition conditions wherein the surface of the silicon thin film on the silicon dioxide is smoothed (e.g., by the CVD method at low temperatures of 600.degree. C. or lower), the epitaxial silicon film grown on the monocrystalline substrate has poor crystallinity, and the characteristics of a device are degraded.
As described above, in the conventional techniques, a silicon film having a smooth surface and good crystallinity cannot be formed on a silicon substrate, a portion of which is exposed and the remaining portion of which is covered with an insulating film. As a result, a miniaturized high-speed MOSFET having a small parasitic capacitance cannot be manufactured.